1. Field of the Invention
The present invention generally relates to an output circuit and, more particularly, to an output circuit provided in a data output section of a semiconductor memory device.
2. Description of the Related Art
An output circuit of a conventional semiconductor memory device is constructed so that a state thereof is shifted from an immediately preceding information outputting state to a state for outputting information at a newly designated address. In such a structure, the information outputting state of the output circuit must be completely changed from a high-level state to a low-level state or vice versa. Such a change in the outputting state is referred to as a full swing. There is a problem in that the full-swing operation tends to generate an undesired noise.
In order to eliminate above-mentioned problem, Japanese Laid-Open Patent Application No.4-67392 discloses a semiconductor memory device in which output pins (output terminals) are short circuited during a high-impedance state when the output thereof is switched so that all of the output pins are set to the same intermediate potential. In this structure, a noise is reduced as compared to that of the full swing since switching operations are always from the intermediate potential. Additionally, Japanese Laid-Open Patent Application No.4-255990 discloses a semiconductor memory device having a circuit for generating an intermediate potential. In this structure, an output pin whose output is to be switched is connected to a point having the intermediate potential output from the intermediate potential output circuit immediately before the output is switched. Further, Japanese Laid-Open Patent Application No.58-194195 discloses an output circuit of a semiconductor memory device provided with a reference voltage and an inverting amplifier in which an output voltage is controlled to be an intermediate potential immediately before the output voltage is switched.
In the techniques disclosed in the above-mentioned patent documents, an output buffer is set in a high-impedance state during a period from an input of an address till a fixation of an output. However, since an intermediate potential between a high-level output voltage V.sub.OH and a low-level output voltage V.sub.OL is provided to the data output terminal, there is a problem in that an output holding time t.sub.OH is decreased. Additionally, if such an intermediate potential value is set, there is a problem in that a current (for example, a current flowing between a P-channel type transistor and an N-channel type transistor of a MOS circuit) flowing in an input part of a circuit which operates upon receipt of a signal from the data output terminal is increased. On the other hand, if a potential value greater than V.sub.OH but smaller than V.sub.CC is set as the intermediate potential value, the problem related to such a current can be eliminated. However, if such an intermediate potential value is set irrespective of immediately preceding data, another problem may occur in that an operation current is increased when the immediately preceding data is low level data and the present data is also low level data since the potential of the output terminal at the low level is once increased to a level higher than V.sub.OH and decreased to the low-level. The same problem also occurs if a value smaller than V.sub.OL and greater than GND is set as the intermediate potential value and if the immediately preceding data is high-level data and the present data is also high-level data.
U.S. Pat. No. 4,604,731 discloses an output circuit for a semiconductor memory device which has a preset circuit connected to a data output terminal so as to adjust the potential of the data output terminal. In this output circuit, a potential level of the data output terminal reaches a high level or a low level by adjusting the potential of the output terminal to a potential intermediate between a first potential supply terminal and a second potential supply terminal during a preset period prior to a data readout from a memory cell. In this structure, an intermediate potential value provided to the output terminal is determined in response to the output value before the address is changed. However, since a preset voltage which determines the preset period is determined by a pulse width of a read control signal, it is difficult to set the intermediate potential to be higher than a high-level potential V.sub.OH or lower than a low-level potential V.sub.OL.